--
-- VHDL Architecture mp3_speler_lib.LCD_display.arch_name
--
-- Created:
--          by - John.UNKNOWN (EPOX)
--          at - 18:20:20 08/20/2004
--
-- using Mentor Graphics HDL Designer(TM) 2004.1 (Build 41)
--
LIBRARY ieee ;
USE ieee.std_logic_1164.ALL ;
USE ieee.std_logic_arith.ALL ;

ENTITY d_LCD_display IS
   PORT( 
      rst : IN     std_logic;
      RS  : IN     std_logic;
      R_W : IN     std_logic;
      E   : IN     std_logic;
      DB  : IN     std_logic_vector (7 DOWNTO 0)
   );

-- Declarations

END d_LCD_display ;

--
ARCHITECTURE arch_name OF d_LCD_display IS




  TYPE RS_DB_TYPE IS ARRAY(0 TO 5000) OF std_logic_vector(8 DOWNTO 0);

  SIGNAL RS_DB_ARRAY : RS_DB_TYPE;

  SIGNAL i : INTEGER RANGE 0 TO 5000;

BEGIN
  
  
  
  PROCESS(rst,E)
    
    TYPE vector_file IS FILE OF std_logic_vector(9 DOWNTO 0);
    FILE     f : vector_file;
    
    BEGIN
      
      
      IF FALLING_EDGE(rst) THEN
        
        
        file_open(f,"LCD_display.lst",write_mode);
        WRITE (f, b"10_0000_0000");
        file_close(f);
        
        i <= 0;
        
        
        
      ELSIF FALLING_EDGE(E) AND R_W = '0' THEN
        
        
        file_open(f,"LCD_display.lst",write_mode);
          FOR j IN 0 TO i-1 LOOP
            WRITE (f, '0' & RS_DB_ARRAY(j));
          END LOOP; 
          WRITE (f, '0' & RS & DB);
        file_close(f); 
        
        RS_DB_ARRAY(i) <= RS & DB;
        i <= i + 1;
        
      END IF; 
 
      
    END PROCESS;
    
 
  
  
  
  
END ARCHITECTURE arch_name;

